In recent years, scaling down in size of MOS transistors has been continuing in accordance with the scaling rule in order to reduce power consumption and improve the operation rate of semiconductor integrated circuit, and moreover suppress manufacturing cost by improving integration density. However, as gate length of a MOS transistor becomes short, a punch-through current flows between the source and the drain even if the transistor is in the off state. The consequence is the so-called “short-channel effect” which causes various problems in the semiconductor integrated circuit.
As an effective means for preventing short-channel effect, formation of a pocket region may be considered. A pocket region is a region formed so as to extrude under the gate from the gate edge of the MOS transistor by implanting an impurity of the same conductivity type as the channel region in high concentration, and this pocket region is provided for suppressing spread of depletion layer at the drain edge.
The pocket region is generally formed as follows. A gate insulating film is formed on a silicon substrate and a polycrystal silicon layer is deposited on the gate insulating film as a gate electrode. Next, after a gate pattern is formed by processing the polycrystal silicon layer, an impurity of the same conductivity type as that of a channel impurity is implanted to the silicon substrate using the gate pattern as a mask. The pocket impurity is generally implanted from a diagonal direction to the substrate surface in view of implanting the impurity to the lower side of the gate pattern. Thereafter, high temperature annealing is performed to activate the impurity.
FIGS. 1(A) and 1(B) are graphs showing the relationship between threshold voltage value (Vth) and gate length of common MOS transistors. FIG. 1(A) shows the characteristic of a nMOS transistor and FIG. 1(B), the characteristic of a pMOS transistor. The vertical axis indicates Vth (V) and the horizontal axis indicates gate length (nm). As demonstrated by these graphs, when the gate length becomes 70 nm or less, both nMOS transistor and pMOS transistor have reduced absolute values of Vth; and subsequently, short-channel effect appears.
FIG. 2 is a graph indicating gate leakage current and overlap capacitance when the MOS transistor manufactured on the basis of the related art is in the off state. The vertical axis indicates leakage current (A/μm) and the horizontal axis indicates overlap capacitance (fF/μm). In this figure, ∇ is the data when Sb is implanted as a pocket impurity, while Δ is the data when B is implanted, ◯ is the data when P is implanted, and □ is the data when In is implanted, respectively. Here, the overlap capacitance means the accumulated capacity of the capacitor formed by the gate insulating film, a gate electrode and an extension region. The extension region is a diffusing region formed by shallow implantation of an impurity of the conductivity type opposite to that of the channel region into the surface of a silicon substrate located under the gate pattern edge.
On the surface of silicon substrate under the gate edge, both pocket impurity and extension impurity exist and these impurities cancel each other, as the impurities have opposite conductivity types.
An object of the present invention is to improve important characteristics of a MOS transistor by improving the processes to form the pocket region.